This invention is directed to a system for equilibrating and precharging bit lines in a semiconductor memory, such as in a RAM (Random Access Memory).
It is a standard practice to equilibrate (short together) and to precharge the bit lines of a semiconductor memory before accessing a memory cell in a column of cells which is coupled to those bit lines. U.S. Pat. Nos. 3,949,385, 4,161,040 and 4,272,832 are illustrative of the various known techniques for effecting such equilibration and precharge. Ser. No. 164,283, entitled "Asynchronously Equilibrated and Pre-Charged Static RAM," filed June 30, 1980, now U.S. Pat. No. 4,355,377 assigned to Inmos Corporation, the assignee of the present invention.
In certain circumstances, conventional techniques for effecting bit line precharge and equilibration can lead to instability in the state of a memory cell and even a loss of data therein. These problems are best explained with reference to FIG. 1 which shows typical circuitry for precharging and equilibrating a pair of bit lines 10 and 12.
The illustrated bit lines are coupled to a column of memory cells which includes cells 14, 16 and a plurality of additional cells (not shown). Column and row select circuitry (also not shown) may be coupled to the bit lines and memory cells for accessing a particular cell in the illustrated column of cells.
Coupled to the top of the bit lines 10 and 12 are an equilibrating transistor 18, precharge transistors 20 and 22, and "keeper" transistors 24 and 26. The gates of transistors 18, 20 and 22 are coupled to a common node 28 which receives a precharge pulse P. This pulse typically goes from zero volts to Vcc for turning on transistors 18, 20 and 22 for a short interval prior to accessing the column. In response to the pulse P, the transistor 18 shorts together bit lines 10 and 12 while transistors 20 and 22 pull both bit lines toward Vcc. At the termination of the pulse P, the bit lines 10 and 12 are intended to be at equal high level potentials. The transistors 24 and 26 merely serve to trickle charge to the bit lines to compensate for charge leakage therefrom.
Under nominal operating conditions, one of the bit lines will be at a relatively low level while the other bit line will be at a relatively higher level. However, transient voltages at the node 28 can cause both bit lines to be pulled to substantially equal low levels. In that condition, the state of the memory cells is unstable and can result in a cell losing its data by flipping to an opposite state due to inherent imbalances in cell construction.
The condition which causes the foregoing problem arises primarily when the pulse P exhibits undesired transients which may be caused by noise and transmission line like reflections. Such transients may result in "glitches" in the pulse P which are exhibited as short duration voltage excursions at the node 28. These transients may also result in the duration of the pulse P being shortened. Whatever the case, the result is that such transients are able to turn on the transistor 18 sufficiently to pull both bit lines to substantially the same low potential, but transistors 20 and 22 are not held on long enough to pull the bit lines to their desired precharge potential. Consequently, both bit lines may be at equal low potentials, thereby causing the memory cells to be in an unstable state.
A general object of the present invention is, therefore, to provide improved precharging and equilibrating circuitry for a semiconductor memory.
It is a more specific object of the invention to provide bit line precharging and equilibrating circuitry which overcomes the drawbacks discussed above and which is no more complex than conventional circuitry.